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<h1><a name="Message">Timing Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Timing Analysis Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\impl\gwsynthesis\lvds_video.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_video.cst</td>
</tr>
<tr>
<td class="label">Timing Constraint File</td>
<td>C:\study\24FPGA\Mini_LED_file\last\Gowin_LVDS_7to1_RX_RefDesign\project\src\lvds_video.sdc</td>
</tr>
<tr>
<td class="label">Tool Version</td>
<td>V1.9.10.02</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW2A-LV55PG484C8/I7</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW2A-55</td>
</tr>
<tr>
<td class="label">Device Version</td>
<td>C</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Sat Nov  9 01:38:09 2024
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2024 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Summary">Timing Summaries</a></h1>
<h2><a name="STA_Tool_Run_Summary">STA Tool Run Summary:</a></h2>
<table class="summary_table">
<tr>
<td class="label">Setup Delay Model</td>
<td>Slow 0.95V 85C C8/I7</td>
</tr>
<tr>
<td class="label">Hold Delay Model</td>
<td>Fast 1.05V 0C C8/I7</td>
</tr>
<tr>
<td class="label">Numbers of Paths Analyzed</td>
<td>6787</td>
</tr>
<tr>
<td class="label">Numbers of Endpoints Analyzed</td>
<td>4124</td>
</tr>
<tr>
<td class="label">Numbers of Falling Endpoints</td>
<td>4</td>
</tr>
<tr>
<td class="label">Numbers of Setup Violated Endpoints</td>
<td>5</td>
</tr>
<tr>
<td class="label">Numbers of Hold Violated Endpoints</td>
<td>0</td>
</tr>
</table>
<h2><a name="Clock_Report">Clock Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">NO.</th>
<th class="label">Clock Name</th>
<th class="label">Type</th>
<th class="label">Period</th>
<th class="label">Frequency(MHz)</th>
<th class="label">Rise</th>
<th class="label">Fall</th>
<th class="label">Source</th>
<th class="label">Master</th>
<th class="label">Objects</th>
</tr>
<tr>
<td>1</td>
<td>eclko</td>
<td>Base</td>
<td>3.422</td>
<td>292.227
<td>0.000</td>
<td>1.711</td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/eclko </td>
</tr>
<tr>
<td>2</td>
<td>I_clk</td>
<td>Base</td>
<td>20.000</td>
<td>50.000
<td>0.000</td>
<td>10.000</td>
<td></td>
<td></td>
<td>I_clk </td>
</tr>
<tr>
<td>3</td>
<td>I_clkin_p</td>
<td>Base</td>
<td>11.976</td>
<td>83.500
<td>0.000</td>
<td>5.988</td>
<td></td>
<td></td>
<td>I_clkin_p </td>
</tr>
<tr>
<td>4</td>
<td>tck_pad_i</td>
<td>Base</td>
<td>50.000</td>
<td>20.000
<td>0.000</td>
<td>25.000</td>
<td></td>
<td></td>
<td>gw_gao_inst_0/tck_ibuf/I </td>
</tr>
<tr>
<td>5</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.251
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>6.843</td>
<td>146.126
<td>0.000</td>
<td>3.422</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>7</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>10.265</td>
<td>97.417
<td>0.000</td>
<td>5.133</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>8</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.000
<td>0.000</td>
<td>20.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>9</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>40.000</td>
<td>25.000
<td>0.000</td>
<td>20.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>10</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>1040.000</td>
<td>0.962
<td>0.000</td>
<td>520.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>11</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>120.000</td>
<td>8.333
<td>0.000</td>
<td>60.000</td>
<td>I_clk_ibuf/I</td>
<td>I_clk</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
<tr>
<td>12</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>11.977</td>
<td>83.493
<td>0.000</td>
<td>5.988</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
<td>eclko</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT </td>
</tr>
<tr>
<td>13</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.227
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT </td>
</tr>
<tr>
<td>14</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Generated</td>
<td>3.422</td>
<td>292.227
<td>0.000</td>
<td>1.711</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP </td>
</tr>
<tr>
<td>15</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Generated</td>
<td>6.844</td>
<td>146.113
<td>0.000</td>
<td>3.422</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD </td>
</tr>
<tr>
<td>16</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Generated</td>
<td>10.266</td>
<td>97.409
<td>0.000</td>
<td>5.133</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3 </td>
</tr>
</table>
<h2><a name="Max_Frequency_Report">Max Frequency Summary:</a></h2>
<table>
<tr>
<th>NO.</th>
<th>Clock Name</th>
<th>Constraint</th>
<th>Actual Fmax</th>
<th>Logic Level</th>
<th>Entity</th>
</tr>
<tr>
<td>1</td>
<td>I_clk</td>
<td>50.000(MHz)</td>
<td>225.910(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>2</td>
<td>I_clkin_p</td>
<td>83.500(MHz)</td>
<td>471.218(MHz)</td>
<td>4</td>
<td>TOP</td>
</tr>
<tr>
<td>3</td>
<td>tck_pad_i</td>
<td>20.000(MHz)</td>
<td>163.998(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>4</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>25.000(MHz)</td>
<td>91.730(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
<tr>
<td>5</td>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>0.962(MHz)</td>
<td>216.891(MHz)</td>
<td>2</td>
<td>TOP</td>
</tr>
<tr>
<td>6</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>83.493(MHz)</td>
<td>131.152(MHz)</td>
<td>6</td>
<td>TOP</td>
</tr>
</table>
<h4>No timing paths to get frequency of eclko!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk!</h4>
<h4>No timing paths to get frequency of LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk!</h4>
<h2><a name="Total_Negative_Slack_Report">Total Negative Slack Summary:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Clock Name</th>
<th class="label">Analysis Type</th>
<th class="label">Endpoints TNS</th>
<th class="label">Number of Endpoints</th>
</tr>
<tr>
<td>eclko</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>eclko</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>I_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>I_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>I_clkin_p</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>I_clkin_p</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>tck_pad_i</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>SPI7001_25M_1M_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUT.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTP.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Setup</td>
<td>0.000</td>
<td>0</td>
</tr>
<tr>
<td>LVDS_7to1_TX_Top_inst/LVDS_TX_rPLL_inst/rpll_inst/CLKOUTD3.default_gen_clk</td>
<td>Hold</td>
<td>0.000</td>
<td>0</td>
</tr>
</table>
<h1><a name="Detail">Timing Details</a></h1>
<h2><a name="All_Path_Slack_Table">Path Slacks Table:</a></h2>
<h3><a name="Setup_Slack_Table">Setup Paths Table</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>1</td>
<td>-3.294</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/CALIB</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>eclko:[R]</td>
<td>1.711</td>
<td>2.486</td>
<td>2.484</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>2</td>
<td>-3.024</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/CALIB</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>eclko:[R]</td>
<td>1.711</td>
<td>2.486</td>
<td>2.213</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>3</td>
<td>-2.826</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/CALIB</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>eclko:[R]</td>
<td>1.711</td>
<td>2.486</td>
<td>2.016</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>4</td>
<td>-2.753</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>eclko:[R]</td>
<td>1.711</td>
<td>2.486</td>
<td>1.942</td>
</tr>
<tr style="color: #FF0000;" class = "error">
<td>5</td>
<td>-2.748</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>eclko:[R]</td>
<td>1.711</td>
<td>2.486</td>
<td>1.937</td>
</tr>
<tr>
<td>6</td>
<td>4.352</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_maxlight_0_0_s/DI[14]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.590</td>
</tr>
<tr>
<td>7</td>
<td>4.373</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_maxlight_0_0_s/DI[15]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.569</td>
</tr>
<tr>
<td>8</td>
<td>4.656</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_10_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.286</td>
</tr>
<tr>
<td>9</td>
<td>4.659</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_7_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.283</td>
</tr>
<tr>
<td>10</td>
<td>4.659</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_6_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.283</td>
</tr>
<tr>
<td>11</td>
<td>4.678</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_5_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.264</td>
</tr>
<tr>
<td>12</td>
<td>4.678</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_4_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.264</td>
</tr>
<tr>
<td>13</td>
<td>4.687</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_3_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.255</td>
</tr>
<tr>
<td>14</td>
<td>4.687</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_1_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.255</td>
</tr>
<tr>
<td>15</td>
<td>4.693</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_9_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.249</td>
</tr>
<tr>
<td>16</td>
<td>4.693</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_2_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.249</td>
</tr>
<tr>
<td>17</td>
<td>4.709</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_8_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.233</td>
</tr>
<tr>
<td>18</td>
<td>4.866</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_maxlight_0_0_s/DI[3]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.076</td>
</tr>
<tr>
<td>19</td>
<td>4.911</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_maxlight_0_0_s/DI[1]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.031</td>
</tr>
<tr>
<td>20</td>
<td>4.921</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_15_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.021</td>
</tr>
<tr>
<td>21</td>
<td>4.921</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_14_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.021</td>
</tr>
<tr>
<td>22</td>
<td>4.936</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_12_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.006</td>
</tr>
<tr>
<td>23</td>
<td>4.936</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_11_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>7.006</td>
</tr>
<tr>
<td>24</td>
<td>4.952</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_7029_DIAREG_G_0_s0/D</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>6.990</td>
</tr>
<tr>
<td>25</td>
<td>5.043</td>
<td>u1/maxlight_maxlight_0_0_s/DO[5]</td>
<td>u1/maxlight_maxlight_0_0_s/DI[12]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>11.977</td>
<td>0.000</td>
<td>6.900</td>
</tr>
</table>
<h3><a name="Hold_Slack_Table">Hold Paths Table</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>0.074</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[2]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.323</td>
</tr>
<tr>
<td>2</td>
<td>0.076</td>
<td>u1/din_6_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[6]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.325</td>
</tr>
<tr>
<td>3</td>
<td>0.076</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[3]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.325</td>
</tr>
<tr>
<td>4</td>
<td>0.198</td>
<td>u1/din_14_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[14]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.447</td>
</tr>
<tr>
<td>5</td>
<td>0.198</td>
<td>u1/din_13_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[13]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.447</td>
</tr>
<tr>
<td>6</td>
<td>0.202</td>
<td>u1/din_9_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[9]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.451</td>
</tr>
<tr>
<td>7</td>
<td>0.213</td>
<td>u1/din_15_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[15]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>8</td>
<td>0.213</td>
<td>u1/din_11_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[11]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>9</td>
<td>0.213</td>
<td>u1/din_5_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[5]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>10</td>
<td>0.213</td>
<td>u1/din_3_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[3]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>11</td>
<td>0.213</td>
<td>u1/din_0_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.462</td>
</tr>
<tr>
<td>12</td>
<td>0.215</td>
<td>u1/index_6_s0/Q</td>
<td>u1/maxlight_maxlight_0_0_s/ADA[10]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.333</td>
</tr>
<tr>
<td>13</td>
<td>0.215</td>
<td>u1/index_0_s0/Q</td>
<td>u1/maxlight_maxlight_0_0_s/ADA[4]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.333</td>
</tr>
<tr>
<td>14</td>
<td>0.225</td>
<td>u1/din_10_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[10]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>15</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[3]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>16</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[2]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>17</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>18</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>19</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>20</td>
<td>0.225</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.474</td>
</tr>
<tr>
<td>21</td>
<td>0.324</td>
<td>u1/din_4_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[4]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.573</td>
</tr>
<tr>
<td>22</td>
<td>0.333</td>
<td>u1/index2_7_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/ADA[11]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.451</td>
</tr>
<tr>
<td>23</td>
<td>0.335</td>
<td>u1/din_7_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[7]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.584</td>
</tr>
<tr>
<td>24</td>
<td>0.335</td>
<td>u1/din_2_s0/Q</td>
<td>u1/inst1/sdpb_inst_0/DI[2]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.584</td>
</tr>
<tr>
<td>25</td>
<td>0.335</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[1]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>0.000</td>
<td>0.584</td>
</tr>
</table>
<h3><a name="Recovery_Slack_Table">Recovery Paths Table</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>2</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>3</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>4</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>5</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>6</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>7</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>8</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>9</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>10</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>11</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>12</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>13</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>14</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>15</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>16</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>17</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>18</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>19</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>20</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_18_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>21</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_19_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>22</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_20_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>23</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_21_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>24</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_22_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
<tr>
<td>25</td>
<td>4.391</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_23_s0/CLEAR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>5.988</td>
<td>0.003</td>
<td>1.559</td>
</tr>
</table>
<h3><a name="Removal_Slack_Table">Removal Paths Table</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<table class="detail_table">
<tr>
<th class="label">Path Number</th>
<th class="label">Path Slack</th>
<th class="label">From Node</th>
<th class="label">To Node</th>
<th class="label">From Clock</th>
<th class="label">To Clock</th>
<th class="label">Relation</th>
<th class="label">Clock Skew</th>
<th class="label">Data Delay</th>
</tr>
<tr>
<td>1</td>
<td>3.360</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/RESET</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>2</td>
<td>3.360</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/RESET</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>3</td>
<td>3.360</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/RESET</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>4</td>
<td>3.360</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/RESET</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>5</td>
<td>3.360</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/RESET</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>6</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>7</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>8</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>9</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>10</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>11</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>12</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_7_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>13</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_0_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>14</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_1_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>15</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_0_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>16</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_6_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>17</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_7_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>18</td>
<td>3.454</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_6_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.509</td>
</tr>
<tr>
<td>19</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>20</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>21</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>22</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>23</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_de_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>24</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_hs_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
<tr>
<td>25</td>
<td>3.459</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
<td>LVDS_7to1_RX_Top_inst/O_vs_s0/CLEAR</td>
<td>I_clkin_p:[R]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
<td>0.000</td>
<td>1.990</td>
<td>1.514</td>
</tr>
</table>
<h2><a name="MIN_PULSE_WIDTH_TABLE">Minimum Pulse Width Table:</a></h2>
<table class="detail_table">
<tr>
<th class="label">Number</th>
<th class="label">Slack</th>
<th class="label">Actual Width</th>
<th class="label">Required Width</th>
<th class="label">Type</th>
<th class="label">Clock</th>
<th class="label">Objects</th>
</tr>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<tr>
<td>1</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_16_s0</td>
</tr>
<tr>
<td>2</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_15_s0</td>
</tr>
<tr>
<td>3</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_14_s0</td>
</tr>
<tr>
<td>4</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_13_s0</td>
</tr>
<tr>
<td>5</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_12_s0</td>
</tr>
<tr>
<td>6</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_9_s0</td>
</tr>
<tr>
<td>7</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_8_s0</td>
</tr>
<tr>
<td>8</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_1_s0</td>
</tr>
<tr>
<td>9</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_0_s2</td>
</tr>
<tr>
<td>10</td>
<td>3.392</td>
<td>4.392</td>
<td>1.000</td>
<td>Low Pulse Width</td>
<td>I_clkin_p</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
</table>
<h2><a name="Timing_Report_by_Analysis_Type">Timing Report By Analysis Type:</a></h2>
<h3><a name="Setup_Analysis">Setup Analysis Report</a></h3>
<h4>Report Command:report_timing -setup -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.294</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>17.062</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.767</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>eclko:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>14.810</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>17.062</td>
<td>2.252</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT56[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>13.688</td>
<td>13.688</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eclko</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>PLL_R[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>13.802</td>
<td>0.114</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT56[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/FCLK</td>
</tr>
<tr>
<td>13.767</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td>13.767</td>
<td>0.000</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT56[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.486</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.252, 90.661%; tC2Q: 0.232, 9.339%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.114, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-3.024</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.791</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.767</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>eclko:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>14.810</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>16.791</td>
<td>1.981</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT18[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>13.688</td>
<td>13.688</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eclko</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>PLL_R[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>13.802</td>
<td>0.114</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT18[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/FCLK</td>
</tr>
<tr>
<td>13.767</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td>13.767</td>
<td>0.000</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT18[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.486</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.981, 89.517%; tC2Q: 0.232, 10.483%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.114, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.826</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.593</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.767</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>eclko:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>14.810</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>16.593</td>
<td>1.784</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT24[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>13.688</td>
<td>13.688</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eclko</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>PLL_R[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>13.802</td>
<td>0.114</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT24[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/FCLK</td>
</tr>
<tr>
<td>13.767</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td>13.767</td>
<td>0.000</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT24[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.486</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.784, 88.490%; tC2Q: 0.232, 11.510%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.114, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.753</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.520</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.767</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>eclko:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>14.810</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>16.520</td>
<td>1.710</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT40[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>13.688</td>
<td>13.688</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eclko</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>PLL_R[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>13.802</td>
<td>0.114</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT40[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/FCLK</td>
</tr>
<tr>
<td>13.767</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td>13.767</td>
<td>0.000</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT40[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.486</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.710, 88.055%; tC2Q: 0.232, 11.945%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.114, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>-2.748</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>16.515</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>13.767</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>eclko:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>14.810</td>
<td>0.232</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/Q</td>
</tr>
<tr>
<td>16.515</td>
<td>1.705</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>IOT42[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/CALIB</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>13.688</td>
<td>13.688</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>eclko</td>
</tr>
<tr>
<td>13.688</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>6</td>
<td>PLL_R[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/LVDS_RX_rPLL_inst/rpll_inst/CLKOUTP</td>
</tr>
<tr>
<td>13.802</td>
<td>0.114</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT42[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/FCLK</td>
</tr>
<tr>
<td>13.767</td>
<td>-0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td>13.767</td>
<td>0.000</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>IOT42[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-2.486</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>1.711</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.705, 88.025%; tC2Q: 0.232, 11.975%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.114, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.352</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.191</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.830</td>
<td>1.226</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C38[0][B]</td>
<td>u1/n1304_s2/I2</td>
</tr>
<tr>
<td>9.385</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R47C38[0][B]</td>
<td style=" background: #97FFFF;">u1/n1304_s2/F</td>
</tr>
<tr>
<td>10.191</td>
<td>0.806</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DI[14]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.833, 24.150%; route: 3.497, 46.074%; tC2Q: 2.260, 29.776%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.373</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.170</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.819</td>
<td>1.215</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R46C38[3][B]</td>
<td>u1/n1303_s2/I2</td>
</tr>
<tr>
<td>9.272</td>
<td>0.453</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R46C38[3][B]</td>
<td style=" background: #97FFFF;">u1/n1303_s2/F</td>
</tr>
<tr>
<td>10.170</td>
<td>0.899</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DI[15]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.731, 22.868%; route: 3.578, 47.275%; tC2Q: 2.260, 29.857%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.656</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.887</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.887</td>
<td>1.099</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R49C38[0][B]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_10_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C38[0][B]</td>
<td>u1/maxlight_7029_DIAREG_G_10_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C38[0][B]</td>
<td>u1/maxlight_7029_DIAREG_G_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.636%; route: 3.231, 44.346%; tC2Q: 2.260, 31.018%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.884</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.884</td>
<td>1.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R49C37[1][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_7_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_7_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.647%; route: 3.228, 44.321%; tC2Q: 2.260, 31.032%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.659</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.884</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.884</td>
<td>1.096</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R49C37[0][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_6_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C37[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_6_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C37[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.647%; route: 3.228, 44.321%; tC2Q: 2.260, 31.032%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.678</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.864</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.864</td>
<td>1.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C38[2][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_5_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C38[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_5_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R47C38[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.712%; route: 3.209, 44.175%; tC2Q: 2.260, 31.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.678</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.864</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.864</td>
<td>1.077</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C38[1][B]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_4_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C38[1][B]</td>
<td>u1/maxlight_7029_DIAREG_G_4_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R47C38[1][B]</td>
<td>u1/maxlight_7029_DIAREG_G_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.712%; route: 3.209, 44.175%; tC2Q: 2.260, 31.114%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.687</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.855</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.855</td>
<td>1.068</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R48C37[0][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_3_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C37[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_3_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C37[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.743%; route: 3.200, 44.105%; tC2Q: 2.260, 31.152%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.687</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.855</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.855</td>
<td>1.068</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R48C37[1][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_1_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_1_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.743%; route: 3.200, 44.105%; tC2Q: 2.260, 31.152%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.850</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.850</td>
<td>1.062</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R49C36[1][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_9_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C36[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_9_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R49C36[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.762%; route: 3.194, 44.061%; tC2Q: 2.260, 31.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.693</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.850</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.850</td>
<td>1.062</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R48C37[2][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_2_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C37[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_2_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C37[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.762%; route: 3.194, 44.061%; tC2Q: 2.260, 31.177%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.709</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.833</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.833</td>
<td>1.046</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R48C36[2][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_8_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C36[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_8_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R48C36[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 24.818%; route: 3.178, 43.935%; tC2Q: 2.260, 31.247%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.866</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.677</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.316</td>
<td>0.712</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C38[3][A]</td>
<td>u1/n1315_s2/I2</td>
</tr>
<tr>
<td>8.871</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C38[3][A]</td>
<td style=" background: #97FFFF;">u1/n1315_s2/F</td>
</tr>
<tr>
<td>9.677</td>
<td>0.806</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.833, 25.905%; route: 2.983, 42.156%; tC2Q: 2.260, 31.939%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.911</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.632</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.830</td>
<td>1.226</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C38[1][A]</td>
<td>u1/n1317_s2/I2</td>
</tr>
<tr>
<td>9.385</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R47C38[1][A]</td>
<td style=" background: #97FFFF;">u1/n1317_s2/F</td>
</tr>
<tr>
<td>9.632</td>
<td>0.247</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.833, 26.069%; route: 2.938, 41.790%; tC2Q: 2.260, 32.142%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.921</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.622</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.622</td>
<td>0.834</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R43C37[2][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_15_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C37[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_15_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R43C37[2][A]</td>
<td>u1/maxlight_7029_DIAREG_G_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 25.566%; route: 2.966, 42.245%; tC2Q: 2.260, 32.189%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.921</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.622</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.622</td>
<td>0.834</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R43C37[1][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_14_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_14_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R43C37[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 25.566%; route: 2.966, 42.245%; tC2Q: 2.260, 32.189%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.607</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.607</td>
<td>0.819</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R46C35[1][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_12_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R46C35[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_12_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R46C35[1][A]</td>
<td>u1/maxlight_7029_DIAREG_G_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 25.620%; route: 2.951, 42.123%; tC2Q: 2.260, 32.257%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.936</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.607</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.607</td>
<td>0.819</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R43C34[0][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_11_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C34[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_11_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R43C34[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 25.620%; route: 2.951, 42.123%; tC2Q: 2.260, 32.257%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.952</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.591</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_7029_DIAREG_G_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.271</td>
<td>0.667</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C36[3][B]</td>
<td>u1/n734_s1/I1</td>
</tr>
<tr>
<td>8.788</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>16</td>
<td>R44C36[3][B]</td>
<td style=" background: #97FFFF;">u1/n734_s1/F</td>
</tr>
<tr>
<td>9.591</td>
<td>0.803</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R44C34[0][A]</td>
<td style=" font-weight:bold;">u1/maxlight_7029_DIAREG_G_0_s0/D</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C34[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_0_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R44C34[0][A]</td>
<td>u1/maxlight_7029_DIAREG_G_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 25.680%; route: 2.935, 41.989%; tC2Q: 2.260, 32.332%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>5.043</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>9.500</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>2.601</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>16</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKB</td>
</tr>
<tr>
<td>4.861</td>
<td>2.260</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DO[5]</td>
</tr>
<tr>
<td>5.273</td>
<td>0.412</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R47C37[2][A]</td>
<td>u1/maxlight_n732_DOAL_G_5_s0/I0</td>
</tr>
<tr>
<td>5.828</td>
<td>0.555</td>
<td>tINS</td>
<td>FF</td>
<td>3</td>
<td>R47C37[2][A]</td>
<td style=" background: #97FFFF;">u1/maxlight_n732_DOAL_G_5_s0/F</td>
</tr>
<tr>
<td>6.881</td>
<td>1.053</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][A]</td>
<td>u1/n735_s37/I1</td>
</tr>
<tr>
<td>7.252</td>
<td>0.371</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s37/COUT</td>
</tr>
<tr>
<td>7.252</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[0][B]</td>
<td>u1/n735_s38/CIN</td>
</tr>
<tr>
<td>7.287</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s38/COUT</td>
</tr>
<tr>
<td>7.287</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][A]</td>
<td>u1/n735_s39/CIN</td>
</tr>
<tr>
<td>7.322</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s39/COUT</td>
</tr>
<tr>
<td>7.322</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[1][B]</td>
<td>u1/n735_s40/CIN</td>
</tr>
<tr>
<td>7.357</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s40/COUT</td>
</tr>
<tr>
<td>7.357</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][A]</td>
<td>u1/n735_s41/CIN</td>
</tr>
<tr>
<td>7.392</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s41/COUT</td>
</tr>
<tr>
<td>7.392</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C36[2][B]</td>
<td>u1/n735_s42/CIN</td>
</tr>
<tr>
<td>7.428</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C36[2][B]</td>
<td style=" background: #97FFFF;">u1/n735_s42/COUT</td>
</tr>
<tr>
<td>7.428</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][A]</td>
<td>u1/n735_s43/CIN</td>
</tr>
<tr>
<td>7.463</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][A]</td>
<td style=" background: #97FFFF;">u1/n735_s43/COUT</td>
</tr>
<tr>
<td>7.463</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[0][B]</td>
<td>u1/n735_s44/CIN</td>
</tr>
<tr>
<td>7.498</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[0][B]</td>
<td style=" background: #97FFFF;">u1/n735_s44/COUT</td>
</tr>
<tr>
<td>7.498</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][A]</td>
<td>u1/n735_s45/CIN</td>
</tr>
<tr>
<td>7.533</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][A]</td>
<td style=" background: #97FFFF;">u1/n735_s45/COUT</td>
</tr>
<tr>
<td>7.533</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[1][B]</td>
<td>u1/n735_s46/CIN</td>
</tr>
<tr>
<td>7.568</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R44C37[1][B]</td>
<td style=" background: #97FFFF;">u1/n735_s46/COUT</td>
</tr>
<tr>
<td>7.568</td>
<td>0.000</td>
<td>tNET</td>
<td>FF</td>
<td>2</td>
<td>R44C37[2][A]</td>
<td>u1/n735_s47/CIN</td>
</tr>
<tr>
<td>7.604</td>
<td>0.035</td>
<td>tINS</td>
<td>FF</td>
<td>18</td>
<td>R44C37[2][A]</td>
<td style=" background: #97FFFF;">u1/n735_s47/COUT</td>
</tr>
<tr>
<td>8.570</td>
<td>0.966</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R46C38[2][B]</td>
<td>u1/n1306_s2/I2</td>
</tr>
<tr>
<td>9.087</td>
<td>0.517</td>
<td>tINS</td>
<td>FF</td>
<td>1</td>
<td>R46C38[2][B]</td>
<td style=" background: #97FFFF;">u1/n1306_s2/F</td>
</tr>
<tr>
<td>9.500</td>
<td>0.413</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/DI[12]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>11.977</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>6</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 1.795, 26.016%; route: 2.845, 41.228%; tC2Q: 2.260, 32.756%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3><a name="Hold_Analysis">Hold Analysis Report</a></h3>
<h4>Report Command:report_timing -hold -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.074</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.164</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C44[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/CLK</td>
</tr>
<tr>
<td>2.042</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>1</td>
<td>R37C44[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_30_s0/Q</td>
</tr>
<tr>
<td>2.164</td>
<td>0.122</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.122, 37.751%; tC2Q: 0.201, 62.249%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.076</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C35[2][A]</td>
<td>u1/din_6_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R47C35[2][A]</td>
<td style=" font-weight:bold;">u1/din_6_s0/Q</td>
</tr>
<tr>
<td>2.166</td>
<td>0.123</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[6]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.076</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.166</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C41[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R47C41[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_23_s0/Q</td>
</tr>
<tr>
<td>2.166</td>
<td>0.123</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[13]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_5_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.123, 37.889%; tC2Q: 0.202, 62.111%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.198</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.288</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_14_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R41C36[0][A]</td>
<td>u1/din_14_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R41C36[0][A]</td>
<td style=" font-weight:bold;">u1/din_14_s0/Q</td>
</tr>
<tr>
<td>2.288</td>
<td>0.245</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[14]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.198</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.288</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_13_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R41C36[1][A]</td>
<td>u1/din_13_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R41C36[1][A]</td>
<td style=" font-weight:bold;">u1/din_13_s0/Q</td>
</tr>
<tr>
<td>2.288</td>
<td>0.245</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[13]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.245, 54.832%; tC2Q: 0.202, 45.168%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.202</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_9_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R47C36[0][A]</td>
<td>u1/din_9_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R47C36[0][A]</td>
<td style=" font-weight:bold;">u1/din_9_s0/Q</td>
</tr>
<tr>
<td>2.292</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[9]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_15_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C37[0][A]</td>
<td>u1/din_15_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R43C37[0][A]</td>
<td style=" font-weight:bold;">u1/din_15_s0/Q</td>
</tr>
<tr>
<td>2.303</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[15]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_11_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R46C35[0][A]</td>
<td>u1/din_11_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R46C35[0][A]</td>
<td style=" font-weight:bold;">u1/din_11_s0/Q</td>
</tr>
<tr>
<td>2.303</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_5_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C35[2][A]</td>
<td>u1/din_5_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R48C35[2][A]</td>
<td style=" font-weight:bold;">u1/din_5_s0/Q</td>
</tr>
<tr>
<td>2.303</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[5]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_3_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C35[0][A]</td>
<td>u1/din_3_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R48C35[0][A]</td>
<td style=" font-weight:bold;">u1/din_3_s0/Q</td>
</tr>
<tr>
<td>2.303</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.213</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.303</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C34[2][A]</td>
<td>u1/din_0_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C34[2][A]</td>
<td style=" font-weight:bold;">u1/din_0_s0/Q</td>
</tr>
<tr>
<td>2.303</td>
<td>0.260</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.260, 56.314%; tC2Q: 0.202, 43.686%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.173</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.959</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/index_6_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R46C38[0][A]</td>
<td>u1/index_6_s0/CLK</td>
</tr>
<tr>
<td>2.042</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R46C38[0][A]</td>
<td style=" font-weight:bold;">u1/index_6_s0/Q</td>
</tr>
<tr>
<td>2.173</td>
<td>0.132</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/ADA[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.959</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.132, 39.591%; tC2Q: 0.201, 60.409%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.215</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.173</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.959</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/index_0_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R46C39[0][A]</td>
<td>u1/index_0_s0/CLK</td>
</tr>
<tr>
<td>2.042</td>
<td>0.201</td>
<td>tC2Q</td>
<td>RF</td>
<td>5</td>
<td>R46C39[0][A]</td>
<td style=" font-weight:bold;">u1/index_0_s0/Q</td>
</tr>
<tr>
<td>2.173</td>
<td>0.132</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td style=" font-weight:bold;">u1/maxlight_maxlight_0_0_s/ADA[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s/CLKA</td>
</tr>
<tr>
<td>1.959</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[12]</td>
<td>u1/maxlight_maxlight_0_0_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.132, 39.591%; tC2Q: 0.201, 60.409%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_10_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C35[0][A]</td>
<td>u1/din_10_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R49C35[0][A]</td>
<td style=" font-weight:bold;">u1/din_10_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[10]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C42[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C42[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_43_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C42[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R43C42[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_42_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_10_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_33_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R44C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_32_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R54[14]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_8_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R46C42[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R46C42[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_27_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[3]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.225</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.315</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C41[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R48C41[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_24_s0/Q</td>
</tr>
<tr>
<td>2.315</td>
<td>0.272</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/DI[0]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R54[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_6_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.272, 57.427%; tC2Q: 0.202, 42.573%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.324</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.414</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_4_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R49C35[2][A]</td>
<td>u1/din_4_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R49C35[2][A]</td>
<td style=" font-weight:bold;">u1/din_4_s0/Q</td>
</tr>
<tr>
<td>2.414</td>
<td>0.371</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[4]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.371, 64.759%; tC2Q: 0.202, 35.241%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.333</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.292</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.959</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/index2_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C35[1][B]</td>
<td>u1/index2_7_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R43C35[1][B]</td>
<td style=" font-weight:bold;">u1/index2_7_s0/Q</td>
</tr>
<tr>
<td>2.292</td>
<td>0.249</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/ADA[11]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>1.959</td>
<td>0.118</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.249, 55.230%; tC2Q: 0.202, 44.770%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.335</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.425</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_7_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R43C36[2][A]</td>
<td>u1/din_7_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R43C36[2][A]</td>
<td style=" font-weight:bold;">u1/din_7_s0/Q</td>
</tr>
<tr>
<td>2.425</td>
<td>0.382</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[7]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.335</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.425</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>u1/din_2_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R48C36[1][B]</td>
<td>u1/din_2_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R48C36[1][B]</td>
<td style=" font-weight:bold;">u1/din_2_s0/Q</td>
</tr>
<tr>
<td>2.425</td>
<td>0.382</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td style=" font-weight:bold;">u1/inst1/sdpb_inst_0/DI[2]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R45[11]</td>
<td>u1/inst1/sdpb_inst_0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>0.335</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>2.425</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>2.090</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R39C43[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/CLK</td>
</tr>
<tr>
<td>2.043</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>1</td>
<td>R39C43[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/data_reg_29_s0/Q</td>
</tr>
<tr>
<td>2.425</td>
<td>0.382</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/DI[1]</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s/CLKA</td>
</tr>
<tr>
<td>2.090</td>
<td>0.249</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>BSRAM_R36[13]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_mem_ctrl/mem_mem_0_7_s</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 0.382, 65.434%; tC2Q: 0.202, 34.566%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3><a name="Recovery_Analysis">Recovery Analysis Report</a></h3>
<h4>Report Command:report_timing -recovery -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C47[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C47[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C47[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_sep_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R37C44[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C44[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R37C44[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C49[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C49[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C49[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R37C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R37C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R37C44[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C44[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R37C44[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C49[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C49[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C49[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C46[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C46[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C46[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C45[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C45[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C45[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C47[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C47[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C47[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C46[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C46[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C46[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_8_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R41C40[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R41C40[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R41C40[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_9_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C43[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C43[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C43[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_10_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C43[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C43[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C43[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_11_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C42[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C42[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C42[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_12_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C42[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C42[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C42[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_13_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C43[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C43[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C43[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_14_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R37C43[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R37C43[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R37C43[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_15_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C39[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_16_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C39[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_17_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_18_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C39[1][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_18_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C39[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_18_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C39[1][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_18_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_19_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C39[0][B]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_19_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_19_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C39[0][B]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_19_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_20_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R35C40[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_20_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C40[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_20_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R35C40[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_20_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_21_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C39[2][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_21_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C39[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_21_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C39[2][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_21_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_22_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R34C39[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_22_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C39[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_22_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R34C39[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_22_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>4.391</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>10.152</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>14.543</td>
</tr>
<tr>
<td class="label">From</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_23_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[F]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>5.988</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>6.318</td>
<td>0.329</td>
<td>tCL</td>
<td>FF</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>8.592</td>
<td>2.274</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R50C44[1][A]</td>
<td>gw_gao_inst_0/u_la0_top/rst_ao_s0/CLK</td>
</tr>
<tr>
<td>8.824</td>
<td>0.232</td>
<td>tC2Q</td>
<td>FF</td>
<td>155</td>
<td>R50C44[1][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/rst_ao_s0/Q</td>
</tr>
<tr>
<td>10.152</td>
<td>1.327</td>
<td>tNET</td>
<td>FF</td>
<td>1</td>
<td>R38C40[0][A]</td>
<td style=" font-weight:bold;">gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_23_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>11.977</td>
<td>11.977</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.977</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>12.306</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>14.578</td>
<td>2.271</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R38C40[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_23_s0/CLK</td>
</tr>
<tr>
<td>14.543</td>
<td>-0.035</td>
<td>tSu</td>
<td></td>
<td>1</td>
<td>R38C40[0][A]</td>
<td>gw_gao_inst_0/u_la0_top/u_ao_match_0/match_bitwise_pre_reg_23_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-0.003</td>
</tr>
<tr>
<td class="label">Setup Relationship </td>
<td>5.988</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.274, 100.000%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.327, 85.123%; tC2Q: 0.232, 14.877%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 2.271, 100.000%</td>
</tr>
</table>
<h3><a name="Removal_Analysis">Removal Analysis Report</a></h3>
<h4>Report Command:report_timing -removal -max_paths 25 -max_common_paths 1</h4>
<h3>Path1</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.986</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>7</td>
<td>IOT42[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT42[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0/PCLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
<tr>
<td>1.986</td>
<td>0.110</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT42[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path2</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.986</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>7</td>
<td>IOT40[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT40[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1/PCLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
<tr>
<td>1.986</td>
<td>0.110</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT40[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path3</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.986</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>7</td>
<td>IOT24[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT24[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2/PCLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
<tr>
<td>1.986</td>
<td>0.110</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT24[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A2</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path4</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.986</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>7</td>
<td>IOT18[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT18[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3/PCLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
<tr>
<td>1.986</td>
<td>0.110</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT18[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst7_IDDRX71A3</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path5</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.360</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.986</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>7</td>
<td>IOT56[A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/RESET</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>IOT56[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A/PCLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
<tr>
<td>1.986</td>
<td>0.110</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>IOT56[A]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst8_IDDRX71A</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path6</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R32C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/slip_s1</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path7</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C37[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C37[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C37[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_5_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path8</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C36[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C36[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C36[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path9</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C36[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C36[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C36[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path10</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C36[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C36[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C36[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_3_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path11</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C37[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R35C37[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R35C37[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_4_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path12</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C30[2][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_r_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C30[2][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_7_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_7_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C30[2][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path13</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C33[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_b_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_0_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_0_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R32C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path14</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C33[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_b_1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R32C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_1_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_1_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R32C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_b_1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path15</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C35[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_g_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C35[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_0_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_0_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C35[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path16</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_g_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_6_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_6_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path17</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_7_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_g_7_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_7_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_7_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_g_7_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path18</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.454</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.340</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_6_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.340</td>
<td>1.307</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C30[2][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_data_r_6_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R20C30[2][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_6_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_6_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R20C30[2][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_data_r_6_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.307, 86.618%; tC2Q: 0.202, 13.382%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path19</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C37[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/clock_word_lock_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path20</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C35[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C35[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/wd_aln_ctl_inst/count_0_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path21</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[2][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[2][A]</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C37[2][A]</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d2_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path22</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C37[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R33C37[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/dphase_lock_d1_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path23</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_de_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[1][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_de_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[1][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_de_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_de_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C33[1][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_de_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path24</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_hs_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[0][B]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_hs_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_hs_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_hs_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C33[0][B]</td>
<td>LVDS_7to1_RX_Top_inst/O_hs_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h3>Path25</h3>
<p><b>Path Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack</td>
<td>3.459</td>
</tr>
<tr>
<td class="label">Data Arrival Time</td>
<td>5.345</td>
</tr>
<tr>
<td class="label">Data Required Time</td>
<td>1.887</td>
</tr>
<tr>
<td class="label">From</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
<tr>
<td class="label">To</td>
<td>LVDS_7to1_RX_Top_inst/O_vs_s0</td>
</tr>
<tr>
<td class="label">Launch Clk</td>
<td>I_clkin_p:[R]</td>
</tr>
<tr>
<td class="label">Latch Clk</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk:[R]</td>
</tr>
</table>
<p><b>Data Arrival Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>1</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>1.922</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>22</td>
<td>IOT56</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>3.831</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R33C34[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
<tr>
<td>4.033</td>
<td>0.202</td>
<td>tC2Q</td>
<td>RR</td>
<td>45</td>
<td>R33C34[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/reset_sync_s0/Q</td>
</tr>
<tr>
<td>5.345</td>
<td>1.312</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[0][A]</td>
<td style=" font-weight:bold;">LVDS_7to1_RX_Top_inst/O_vs_s0/CLEAR</td>
</tr>
</table>
<p><b>Data Required Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th class="label">FANOUT</th>
<th class="label">LOC</th>
<th>NODE</th>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>0.000</td>
<td>0.000</td>
<td></td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT.default_gen_clk</td>
</tr>
<tr>
<td>0.329</td>
<td>0.329</td>
<td>tCL</td>
<td>RR</td>
<td>444</td>
<td>TOPSIDE[0]</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/Inst6_CLKDIVC/CLKOUT</td>
</tr>
<tr>
<td>1.841</td>
<td>1.511</td>
<td>tNET</td>
<td>RR</td>
<td>1</td>
<td>R34C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_vs_s0/CLK</td>
</tr>
<tr>
<td>1.876</td>
<td>0.035</td>
<td>tUnc</td>
<td></td>
<td></td>
<td></td>
<td>LVDS_7to1_RX_Top_inst/O_vs_s0</td>
</tr>
<tr>
<td>1.887</td>
<td>0.011</td>
<td>tHld</td>
<td></td>
<td>1</td>
<td>R34C33[0][A]</td>
<td>LVDS_7to1_RX_Top_inst/O_vs_s0</td>
</tr>
</table>
<p><b>Path Statistics:</b></p>
<table class="summary_table">
<tr>
<td class="label">Clock Skew</td>
<td>-1.990</td>
</tr>
<tr>
<td class="label">Hold Relationship </td>
<td>0.000</td>
</tr>
<tr>
<td class="label">Logic Level</td>
<td>1</td>
</tr>
<tr>
<td class="label">Arrival Clock Path Delay</td>
<td>cell: 1.922, 50.181%; route: 1.908, 49.819%</td>
</tr>
<tr>
<td class="label">Arrival Data Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.312, 86.662%; tC2Q: 0.202, 13.338%</td>
</tr>
<tr>
<td class="label">Required Clock Path Delay</td>
<td>cell: 0.000, 0.000%; route: 1.511, 100.000%</td>
</tr>
</table>
<h2><a name="Minimum_Pulse_Width_Report">Minimum Pulse Width Report:</a></h2>
<h4>Report Command:report_min_pulse_width -nworst 10 -detail</h4>
<h3>MPW1</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_16_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_16_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_16_s0/CLK</td>
</tr>
</table>
<h3>MPW2</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_15_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_15_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_15_s0/CLK</td>
</tr>
</table>
<h3>MPW3</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_14_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_14_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_14_s0/CLK</td>
</tr>
</table>
<h3>MPW4</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_13_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_13_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_13_s0/CLK</td>
</tr>
</table>
<h3>MPW5</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_12_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_12_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_12_s0/CLK</td>
</tr>
</table>
<h3>MPW6</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_9_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_9_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_9_s0/CLK</td>
</tr>
</table>
<h3>MPW7</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_8_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_8_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_8_s0/CLK</td>
</tr>
</table>
<h3>MPW8</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_1_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_1_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_1_s0/CLK</td>
</tr>
</table>
<h3>MPW9</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_0_s2</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_0_s2/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/delay_count_0_s2/CLK</td>
</tr>
</table>
<h3>MPW10</h3>
<p><b>MPW Summary:</b></p>
<table class="summary_table">
<tr>
<td class="label">Slack:</td>
<td>3.392</td>
</tr>
<tr>
<td class="label">Actual Width:</td>
<td>4.392</td>
</tr>
<tr>
<td class="label">Required Width:</td>
<td>1.000</td>
</tr>
<tr>
<td class="label">Type:</td>
<td>Low Pulse Width</td>
</tr>
<tr>
<td class="label">Clock:</td>
<td>I_clkin_p</td>
</tr>
<tr>
<td class="label"> Objects:</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0</td>
</tr>
</table>
<p><b>Late clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>5.988</td>
<td>0.000</td>
<td>tCL</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>8.477</td>
<td>2.489</td>
<td>tINS</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>11.415</td>
<td>2.938</td>
<td>tNET</td>
<td>FF</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
</table>
<p><b>Early clock Path:</b></p>
<table class="detail_table">
<tr>
<th class="label">AT</th>
<th class="label">DELAY</th>
<th class="label">TYPE</th>
<th class="label">RF</th>
<th>NODE</th>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>active clock edge time</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td></td>
<td></td>
<td>I_clkin_p</td>
</tr>
<tr>
<td>11.976</td>
<td>0.000</td>
<td>tCL</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/I</td>
</tr>
<tr>
<td>13.898</td>
<td>1.922</td>
<td>tINS</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/lvds_71_rx/IB_clk_inst/O</td>
</tr>
<tr>
<td>15.807</td>
<td>1.908</td>
<td>tNET</td>
<td>RR</td>
<td>LVDS_7to1_RX_Top_inst/reset_sync_s0/CLK</td>
</tr>
</table>
<h2><a name="High_Fanout_Nets_Report">High Fanout Nets Report:</a></h2>
<h4>Report Command:report_high_fanout_nets -max_nets 10</h4>
<table class="detail_table">
<tr>
<th class="label">FANOUT</th>
<th class="label">NET NAME</th>
<th class="label">WORST SLACK</th>
<th class="label">MAX DELAY</th>
</tr>
<tr>
<td>444</td>
<td>u1_49</td>
<td>-3.294</td>
<td>2.274</td>
</tr>
<tr>
<td>387</td>
<td>control0[0]</td>
<td>43.902</td>
<td>2.925</td>
</tr>
<tr>
<td>371</td>
<td>clk25M</td>
<td>33.050</td>
<td>2.274</td>
</tr>
<tr>
<td>215</td>
<td>clk1M</td>
<td>37.113</td>
<td>2.274</td>
</tr>
<tr>
<td>192</td>
<td>data96_reg_95_8</td>
<td>17.058</td>
<td>1.191</td>
</tr>
<tr>
<td>155</td>
<td>rst_ao</td>
<td>4.391</td>
<td>1.327</td>
</tr>
<tr>
<td>104</td>
<td>cntlatch_6_8</td>
<td>1035.792</td>
<td>1.054</td>
</tr>
<tr>
<td>104</td>
<td>state_cnt[7]</td>
<td>33.050</td>
<td>2.244</td>
</tr>
<tr>
<td>103</td>
<td>n2054_14</td>
<td>16.569</td>
<td>1.169</td>
</tr>
<tr>
<td>103</td>
<td>sdbpflag_Z</td>
<td>36.440</td>
<td>2.693</td>
</tr>
</table>
<h2><a name="Route_Congestions_Report">Route Congestions Report:</a></h2>
<h4>Report Command:report_route_congestion -max_grids 10</h4>
<table class="detail_table">
<tr>
<th class="label">GRID LOC</th>
<th class="label">ROUTE CONGESTIONS</th>
</tr>
<tr>
<td>R39C56</td>
<td>86.11%</td>
</tr>
<tr>
<td>R46C50</td>
<td>86.11%</td>
</tr>
<tr>
<td>R40C36</td>
<td>86.11%</td>
</tr>
<tr>
<td>R40C46</td>
<td>86.11%</td>
</tr>
<tr>
<td>R41C46</td>
<td>86.11%</td>
</tr>
<tr>
<td>R51C43</td>
<td>86.11%</td>
</tr>
<tr>
<td>R35C42</td>
<td>84.72%</td>
</tr>
<tr>
<td>R35C57</td>
<td>84.72%</td>
</tr>
<tr>
<td>R38C48</td>
<td>84.72%</td>
</tr>
<tr>
<td>R38C53</td>
<td>84.72%</td>
</tr>
</table>
<h2><a name="Timing_Exceptions_Report">Timing Exceptions Report:</a></h2>
<h3><a name="Setup_Analysis_Exceptions">Setup Analysis Report</a></h3>
<h4>Report Command:report_exceptions -setup -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Hold_Analysis_Exceptions">Hold Analysis Report</a></h3>
<h4>Report Command:report_exceptions -hold -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Recovery_Analysis_Exceptions">Recovery Analysis Report</a></h3>
<h4>Report Command:report_exceptions -recovery -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h3><a name="Removal_Analysis_Exceptions">Removal Analysis Report</a></h3>
<h4>Report Command:report_exceptions -removal -max_paths 5 -max_common_paths 1</h4>
<h4>No timing exceptions to report!</h4>
<h2><a name="SDC_Report">Timing Constraints Report:</a></h2>
<table class="detail_table">
<tr>
<th class="label">SDC Command Type</th>
<th class="label">State</th>
<th class="label">Detail Command</th>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name eclko -period 3.422 -waveform {0 1.711} [get_nets {LVDS_7to1_RX_Top_inst/lvds_71_rx/eclko}] -add</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name I_clk -period 20 -waveform {0 10} [get_ports {I_clk}] -add</td>
</tr>
<tr>
<td>TC_CLOCK</td>
<td>Actived</td>
<td>create_clock -name I_clkin_p -period 11.976 -waveform {0 5.988} [get_ports {I_clkin_p}] -add</td>
</tr>
</table>
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